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general description the max1214n is a monolithic, 12-bit, 210msps ana- log-to-digital converter (adc) optimized for outstanding dynamic performance at high-if frequencies beyond 300mhz. the product operates with conversion rates up to 210msps while consuming only 799mw. at 210msps and an input frequency up to 100mhz, the max1214n achieves an 81.3dbc spurious-free dynam- ic range (sfdr) with excellent 67db signal-to-noise ratio (snr) that remains flat (within 2db) for input tones up to 250mhz. this makes it ideal for wideband appli- cations such as communications receivers, cable-head end receivers, and power-amplifier predistortion in cel- lular base-station transceivers. the max1214n operates from a single 1.8v power sup- ply. the analog input is designed for ac-coupled differ- ential or single-ended operation. the adc also features a selectable on-chip divide-by-2 clock circuit that accepts clock frequencies as high as 420mhz. a low- voltage differential signal (lvds) sampling clock is rec- ommended for best performance. the converter provides lvds-compatible digital outputs with data for- mat selectable to be either two? complement or offset binary. the max1214n is available in a 68-pin qfn package with exposed paddle (ep) and is specified over the industrial (-40? to +85?) temperature range. see the pin-compatible versions table for a complete selection of 8-bit, 10-bit, and 12-bit high-speed adcs inthis family. applications base-station power-amplifier linearizationcable-head end receivers wireless and wired broadband communications communications test equipment radar and satellite subsystems features ? 210msps conversion rate ? excellent low-noise characteristics snr = 67db at f in = 100mhz snr = 65db at f in = 250mhz ? excellent dynamic range sfdr = 81.3dbc at f in = 100mhz sfdr = 84.9dbc at f in = 250mhz ? single 1.8v supply ? 799mw power dissipation at f sample = 210msps and f in = 100mhz ? on-chip track-and-hold amplifier ? internal 1.24v-bandgap reference ? on-chip selectable divide-by-2 clock input ? lvds digital outputs with data clock output ? max1214nevkit available max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications ________________________________________________________________ maxim integrated products 1 19-3866; rev 0; 4/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available pin-compatible versions part resolution (bits) speed grade (m sps) on-chip buffer max1121 8 250 yes max1122 10 170 yes max1123 10 210 yes max1124 10 250 yes max1213 12 170 yes max1214 12 210 yes max1215 12 250 yes max1213n 12 170 no max1214n 12 210 no max1215n 12 250 no pin configuration appears at end of data sheet. part temp range pin- package pkgcode max1214negk-d -40 c to +85 c 68 qfn-ep* g6800-4 max1214negk+d -40 c to +85 c 68 qfn-ep* g6800-4 ordering information * ep = exposed paddle. + denotes lead-free package. d = dry pack. downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 210mhz, differential clock input drive, 0.1? capacitor on refio, internal ref- erence, digital output pins differential r l = 100 ? . limits are for t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc to agnd ......................................................-0.3v to +2.1v ov cc to ognd .....................................................-0.3v to +2.1v av cc to ov cc .......................................................-0.3v to +2.1v agnd to ognd ....................................................-0.3v to +0.3v inp, inn to agnd ....................................-0.3v to (av cc + 0.3v) all digital inputs to agnd........................-0.3v to (av cc + 0.3v) refio, refadj to agnd ........................-0.3v to (av cc + 0.3v) all digital outputs to ognd ....................-0.3v to (ov cc + 0.3v) current into any pin..........................................................?0ma continuous power dissipation (t a = +70?, multilayer board) 68-pin qfn-ep (derate 41.7mw/? above +70?)....3333mw operating temperature range ...........................-40? to +85? junction temperature .....................................................+150? storage temperature range ............................-60? to +150? lead temperature (soldering,10s) ..................................+300? parameter symbol conditions min typ max units dc accuracy resolution 12 bits integral nonlinearity inl f in = 10mhz (note 2) -2.1 0.75 +2.1 lsb differential nonlinearity dnl no missing codes (note 2) -1.0 0.3 +1.3 lsb transfer curve offset v os (note 2) -3 +3 mv offset temperature drift 15 ?/ c analog inputs (inp, inn) full-scale input voltage range v fs 1150 1390 mv p-p full-scale range temperaturedrift 60 ppm/ c common-mode input voltage v cm internally self-biased 0.7 v differential input capacitance c in 2.5 pf differential input resistance r in 1.8 k ? full-power analog bandwidth fpbw 700 mhz reference (refio, refadj) reference output voltage v refio refadj = agnd 1.18 1.24 1.30 v reference temperature drift 90 ppm/ c refadj input high voltage v refadj used to disable the internal reference av cc - 0.3 v sampling characteristics maximum sampling rate f sample 210 mhz minimum sampling rate f sample 20 mhz clock duty cycle set by clock-management circuit 40 to 60 % aperture delay t ad figures 5, 11 620 ps aperture jitter t aj figure 11 0.15 ps rms downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications _______________________________________________________________________________________ 3 electrical characteristics (continued)(av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 210mhz, differential clock input drive, 0.1? capacitor on refio, internal ref- erence, digital output pins differential r l = 100 ? . limits are for t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units clock inputs (clkp, clkn) differential clock input amplitude (note 3) 200 500 mv p-p clock input common-modevoltage range internally self-biased 1.15 ?.25 v clock differential input r clk 11 ?5% k ? clock differential inputcapacitance c clk 5p f dynamic characteristics (at a in = -1dbfs) f in = 10mhz 65.5 67.3 f in = 100mhz 65.2 67 f in = 200mhz 65.3 signal-to-noise ratio snr f in = 250mhz 65.0 db f in = 10mhz 65.3 67.2 f in = 100mhz 64.9 66.6 f in = 200mhz 65.2 signal-to-noise and distortion sinad f in = 250mhz 64.9 db f in = 10mhz 77.0 88.5 f in = 100mhz 76.0 81.3 f in = 200mhz 82.8 spurious-free dynamic range sfdr f in = 250mhz 84.9 dbc f in = 10mhz -88.5 -77.0 f in = 100mhz -81.3 -76.0 f in = 200mhz -82.8 worst harmonics(hd2 or hd3) f in = 250mhz -84.9 dbc two-tone intermodulationdistortion ttimd f in1 = 97mhz at -7dbfs, f in2 = 100mhz at -7dbfs -79 dbc lvds digital outputs (d0p/n?11p/n, orp/n) differential output voltage |v od |r l = 100 ? 280 440 mv output offset voltage ov os r l = 100 ? 1.110 1.370 v downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications 4 _______________________________________________________________________________________ electrical characteristics (continued)(av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 210mhz, differential clock input drive, 0.1? capacitor on refio, internal ref- erence, digital output pins differential r l = 100 ? . limits are for t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units lvcmos digital inputs (clkdiv, t /b) digital input-voltage low v il 0.2 x av cc v digital input-voltage high v ih 0.8 x av cc v timing characteristics clk-to-data propagation delay t pdl figure 5 2.05 ns clk-to-dclk propagation delay t cpdl figure 5 3.95 ns dclk-to-data propagation delay t cpdl - t pdl figure 5 (note 3) 1.8 1.9 2.0 ns lvds output rise time t rise 20% to 80%, c l = 5pf 450 ps lvds output fall time t fall 20% to 80%, c l = 5pf 450 ps output data pipeline delay t latency figure 5 11 clock cycles power requirements analog supply voltage range av cc 1.70 1.80 1.90 v digital supply voltage range ov cc 1.70 1.80 1.90 v analog supply current i avcc f in = 100mhz 379 410 ma digital supply current i ovcc f in = 100mhz 65 71 ma analog power dissipation p diss f in = 100mhz 799 866 mw offset 1.8 mv/v power-supply rejection ratio(note 4) psrr gain 1.5 %fs/v note 1: values at t a +25? guaranteed by production test, values at t a < +25? guaranteed by design and characterization. note 2: static linearity and offset parameters are computed from an end-point curve fit. note 3: parameter guaranteed by design and characterization: t a = -40? to +85?. note 4: psrr is measured with both analog and digital supplies connected to the same potential. downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications _______________________________________________________________________________________ 5 fft plot (8192-point data record) max1214n toc01 amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 f sample = 210mhz f in = 12.484mhz a in = -0.97dbfs snr = 67.3dbsinad = 67.2db thd = -83.4dbc sfdr = 88.5db hd2 = -90.4dbc hd3 = -96.7dbc 3 2 5 4 010203 0405060708090100 analog input frequency (mhz) fft plot (8192-point data record) max1214n toc02 amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 2 3 5 010203 0405060708090100 analog input frequency (mhz) 4 f sample = 210mhz f in = 100.155mhz a in = -0.954dbfs snr = 67dbsinad = 66.6db thd = -76.8dbc sfdr = 81.2dbc hd2 = -81.2dbc hd3 = -81.8dbc fft plot (8192-point data record) max1214n toc03 amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 f sample = 210mhz f in = 199.771mhz a in = -0.961dbfs snr = 65.4dbsinad = 65.1db thd = -78.5dbc sfdr = 82.8dbc hd2 = -82.8dbc hd3 = -84.6dbc 3 2 010203 0405060708090100 analog input frequency (mhz) 6 7 9 8 5 4 10 fft plot (8192-point data record) max1214n toc04 amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 f sample = 210mhz f in = 249.913mhz a in = -0.994dbfs snr = 65dbsinad = 64.9db thd = -79.3dbc sfdr = 85dbc hd2 = -85dbc hd3 = -86dbc 3 2 010203 0405060708090100 analog input frequency (mhz) 5 4 two-tone imd plot (8192-point data record) max1214n toc05 amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 f sample = 210mhz f in1 = 96.8737793mhz f in2 = 100.1550293mhz imd = -79dbc f in1 f in2 2f in2 - f in1 2f in1 + f in2 2f in2 + f in1 f in2 - f in1 f in2 + f in1 010203 0405060708090100 analog input frequency (mhz) snr/sinad vs. analog input frequency (f sample = 210mhz, a in = -1dbfs) max1214n toc06 f in (mhz) snr/sinad (db) 250 200 150 100 50 50 55 60 65 7045 0 300 snr sinad sfdr/(-thd) vs. analog input frequency (f sample = 210mhz, a in = -1dbfs) max1214n toc07 f in (mhz) sfdr/(-thd) (dbc) 250 200 150 100 50 50 55 60 65 70 75 80 85 90 95 100 45 0 300 sfdr -thd hd2/hd3 vs. analog input frequency (f sample = 210mhz, a in = -1dbfs) max1214n toc08 f in (mhz) hd2/hd3 (dbc) 250 200 150 100 50 -105 -95 -100 -90 -85 -80 -75 -70 -65 -60 -55 -50 -110 0 300 hd2 hd3 snr/sinad vs. analog input amplitude (f sample = 210mhz, f in = 65.087mhz) max1214n toc9 analog input amplitude (dbfs) snr/sinad (db) -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 20 30 40 50 60 70 0 10 -55 0 snr sinad t ypical operating characteristics (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 210mhz, a in = -1dbfs; see each toc for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 ? , t a = +25?.) downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications 6 ______________________________________________________________________________________ sfdr/(-thd) vs. analog input amplitude (f sample = 210mhz, f in = 65.087mhz) max1214n toc10 analog input amplitude (dbfs) sfdr/(-thd) (dbc) -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 45 60 70 80 9055 65 75 85 95 100 30 35 5040 -55 0 sfdr -thd hd2/hd3 vs. analog input amplitude (f sample = 210mhz, f in = 65.087mhz) max1214n toc11 analog input amplitude (dbfs) hd2/hd3 (dbc) -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -90 -80 -70 -60 -50 -40 -30 -110 -100 -55 0 hd2 hd2 snr/sinad vs. sample frequency (f in = 65.087mhz, a in = -1dbfs) max1214n toc12 f sample (mhz) snr/sinad (db) 180 200 160 120 140 100 40 60 80 20 55 60 65 70 7540 5045 0 220 snr sinad sfdr/(-thd) vs. sample frequency (f in = 65.087mhz, a in = -1dbfs) max1214n toc13 f sample (mhz) sfdr/(-thd) (dbc) 180 200 160 120 140 60 80 100 40 20 75 80 85 90 95 100 50 7065 60 55 0 220 sfdr -thd hd2/hd3 vs. sample frequency (f in = 65.087mhz, a in = -1dbfs) max1214n toc14 f sample (mhz) hd2/hd3 (dbc) 180 200 160 140 120 100 60 80 20 40 -100-110 -95 -90 -85 -80 -75 -70 -60-65 -120 -105-115 0 220 hd3 hd2 total power dissipation vs. sample frequency (f in = 65.087mhz, a in = -1dbfs) max1214n toc15 f sample (mhz) p diss (w) 191 153 172 134 96 115 58 77 39 0.7500.725 0.775 0.800 0.825 0.850 0.8750.700 20 210 integral nonlinearity vs. digital output code max1214n toc16 digital output code inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.4 -0.1 0.2 0.5 0.8 -0.7 0 4096 differential nonlinearity vs. digital output code max1214n toc17 digital output code dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.5 -0.2 0.1 0.4 0.7 -0.8 0 4096 gain bandwidth plot (f sample = 210mhz, a in = -1dbfs) max1214n toc18 analog input frequency (mhz) gain (db) 10 100 -6 -5 -4 -3 -2 -1 0 1 -7 1 1000 t ypical operating characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 210mhz, a in = -1dbfs; see each toc for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 ? , t a = +25?.) downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications _______________________________________________________________________________________ 7 snr/sinad vs. temperature (f sample = 210mhz, f in = 100mhz, a in = -1dbfs) max1214n toc19 temperature ( c) snr/sinad (db) 60 35 10 -15 61.5 62.5 63.5 64.5 65.5 66.5 67.5 68.5 69.5 70.560.5 -40 85 snr sinad sfdr/(-thd) vs. temperature (f sample = 210mhz, f in = 100mhz, a in = -1dbfs) max1214n toc20 temperature ( c) sfdr/(-thd) (dbc) 60 35 10 -15 65 70 75 80 85 9060 -40 85 sfdr -thd hd2/hd3 vs. temperature (f sample = 210mhz, f in = 100mhz, a in = -1dbfs) max1214n toc21 temperature ( c) hd2/hd3 (dbc) 60 35 10 -15 55 60 65 70 75 80 85 90 95 100 50 -40 85 hd2 hd3 snr/sinad vs. supply voltage (f in = 65.087mhz, a in = -1dbfs) max1214n toc22 supply voltage (v) snr/sinad (db) 1.85 1.80 1.75 6261 63 64 65 6867 66 69 7060 1.70 1.90 snr sinad t ypical operating characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 210mhz, a in = -1dbfs; see each toc for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 ? , t a = +25?.) sfdr/(-thd) vs. supply voltage (f in = 65.087mhz, a in = -1dbfs) max1214n toc23 supply voltage (v) sfdr/(-thd) (dbc) 1.85 1.80 1.75 73 76 79 82 85 88 91 94 97 100 70 1.70 1.90 sfdr -thd hd2/hd3 vs. supply voltage (f in = 65.087mhz, a in = -1dbfs) max1214n toc24 supply voltage (v) hd2/hd3 (dbc) 1.85 1.80 1.75 -115 -110 -105 -100 -95 -90 -85 -80 -75 -70 -120 1.70 1.90 hd3 hd2 t ypical operating characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 210mhz, a in = -1dbfs; see each toc for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 ? , t a = +25?.) reference voltage vs. supply voltage (f in = 65.087mhz, a in = -1dbfs) max1214n toc25 supply voltage (v) v refio (v) 1.85 1.80 1.75 1.2421.241 1.243 1.2461.245 1.244 1.247 1.2481.240 1.70 1.90 downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications 8 _______________________________________________________________________________________ pin description pin name function 1, 6, 11?4, 20, 25, 62, 63, 65 av cc analog supply voltage. bypass av cc to agnd with a parallel combination of 0.1? and 0.22? capacitors for best decoupling results. connect all av cc inputs together. see the grounding, bypassing, and board layout considerations section. 2, 5, 7, 10, 15, 16, 18, 19, 21, 24, 64, 66, 67 agnd analog converter ground. connect all agnd inputs together. 3 refio reference input/output. pull refadj high to allow refio to accept an external reference. pullrefadj low to activate the internal 1.24v-bandgap reference. connect a 0.1? capacitor from refio to agnd for both internal and external reference. 4 refadj reference adjust input. refadj allows for fsr adjustments by placing a resistor or trimpotentiometer between refadj and agnd (decreases fsr) or refadj and refio (increases fsr). connect refadj to av cc to override the internal reference with an external source connected to refio. connect refadj to agnd to allow the internal reference to determine thefsr of the data converter. see the fsr adjustment using the internal bandgap reference section. 8i np positive analog input terminal. internally self-biased to 0.7v. 9 inn negative analog input terminal. internally self-biased to 0.7v. 17 clkdiv clock divider input. clkdiv controls the sampling frequency relative to the input clock frequency. clkdiv has an internal pulldown resistor. clkdiv = 0: sampling frequency is at one-half the input clock frequency. clkdiv = 1: sampling frequency is equal to the input clock frequency. 22 clkp tr ue c l ock inp ut. ap p l y an lv d s - com p ati b l e i np ut l evel to c lkp . inter nal l y sel f- b i ased to 1.15v . 23 clkn complementary clock input. apply an lvds-compatible input level to clkn. internally self-biased to 1.15v. 26, 45, 61 ognd digital converter ground. ground connection for digital circuitry and output drivers. connect allognd inputs together. 27, 28, 41, 44, 60 ov cc digital supply voltage. bypass ov cc with a 0.1? capacitor to ognd. connect all ov cc inputs together. see the grounding, bypassing, and board layout considerations section. 29 d0n complementary output bit 0 (lsb) 30 d0p true output bit 0 (lsb) 31 d1n complementary output bit 1 32 d1p true output bit 1 33 d2n complementary output bit 2 34 d2p true output bit 2 35 d3n complementary output bit 3 36 d3p true output bit 3 downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications _______________________________________________________________________________________ 9 pin description (continued) pin name function 37 d4n complementary output bit 4 38 d4p true output bit 4 39 d5n complementary output bit 5 40 d5p true output bit 5 42 dclkn complementary clock output. this output provides an lvds-compatible output level and canbe used to synchronize external devices to the converter clock. 43 dclkp true clock output. this output provides an lvds-compatible output level and can be used tosynchronize external devices to the converter clock. 46 d6n complementary output bit 6 47 d6p true output bit 6 48 d7n complementary output bit 7 49 d7p true output bit 7 50 d8n complementary output bit 8 51 d8p true output bit 8 52 d9n complementary output bit 9 53 d9p true output bit 9 54 d10n complementary output bit 10 55 d10p true output bit 10 56 d11n complementary output bit 11 (msb) 57 d11p true output bit 11 (msb) 58 orn complementary out-of-range control bit output. if an out-of-range condition is detected,bit orn flags this condition by transitioning low. 59 orp true out-of-range control bit output. if an out-of-range condition is detected, bit orp flagsthis condition by transitioning high. 68 t /b output format select. this lvcmos-compatible input controls the digital output format of themax1214n. t /b has an internal pulldown resistor. t /b = 0: two?-complement output format. t /b = 1: binary output format. ? p exposed paddle. the exposed paddle is located on the backside of the chip and must beconnected to agnd. downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications 10 ______________________________________________________________________________________ detailed description theory of operation the max1214n uses a fully differential pipelined archi-tecture that allows for high-speed conversion, opti- mized accuracy, and linearity while minimizing power consumption. both positive (inp) and negative/complementary ana- log input terminals (inn) are centered around a 0.7v common-mode voltage, and accept a differential ana- log input voltage swing of v fs / 4 each, resulting in a typical 1.39v p-p differential full-scale signal swing. inputs inp and inn are sampled when the differentialsampling clock signal transitions high. when using the clock-divide mode, the analog inputs are sampled at every other high transition of the differential sam- pling clock. each pipeline converter stage converts its input voltage to a digital output code. at every stage, except the last, the error between the input voltage and the digital out- put code is multiplied and passed along to the next pipeline stage. digital error correction compensates foradc comparator offsets in each pipeline stage and ensures no missing codes. the result is a 12-bit parallel digital output word in user-selectable two?-complement or offset binary output formats with lvds-compatible output levels. see figure 1 for a more detailed view of the max1214n architecture. analog inputs (inp, inn) inp and inn are the fully differential inputs of themax1214n. differential inputs usually feature good rejection of even-order harmonics, which allows for enhanced ac performance as the signals are progress- ing through the analog stages. the max1214n analog inputs are self-biased at a 0.7v common-mode voltage and allow a 1.39v p-p differential input voltage swing (figure 2). both inputs are self-biased through 900 ? resistors, resulting in a typical differential input resis- tance of 1.8k ? . drive the analog inputs of the max1214n in ac-coupled configuration to achieve thebest dynamic performance. see the transformer- coupled, differential analog input drive section. max1214n av cc 900 ? 900 ? d0p/n dclkp dclkn d1p/n d2p/n lvds data port ov cc agnd ognd t/h 12-bit pipeline adc clock management reference common- mode buffer clkdiv clkn clkp refadj refio inp inn div1/div2 d11p/n orp/orn t/b figure 1. block diagram downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications ______________________________________________________________________________________ 11 max1214n 12-bit pipeline adc c s from clock-management block t/h to common mode c s c p inp inp inp - inn v cm + v fs / 4 v cm - v fs / 4 +v fs / 2 -v fs / 2 gnd gnd v cm inn inn c s is the sampling capacitance. c p is the parasitic capacitance ~ 1pf. av cc 900 ? 900 ? c p 1.39v differential fsr figure 2. simplified analog input architecture and allowable input voltage range downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications 12 ______________________________________________________________________________________ on-chip reference circuit the max1214n features an internal 1.24v-bandgap refer- ence circuit (figure 3), which, in combination with an internal reference-scaling amplifier, determines the fsr of the max1214n. bypass refio with a 0.1? capacitor to agnd. to compensate for gain errors or increase/de- crease the adc? fsr, the voltage of this bandgap refer- ence can be indirectly adjusted by adding an external resistor (e.g., 100k ? trim potentiometer) between refadj and agnd or refadj and refio. see the applications information section for a detailed description of this process.to disable the internal reference, connect refadj to av cc . apply an external, stable reference to set the converter? full scale. to enable the internal reference,connect refadj to agnd. clock inputs (clkp, clkn) drive the clock inputs of the max1214n with an lvds- orlvpecl-compatible clock to achieve the best dynamic performance. the clock signal source must be of high quality and low phase noise to avoid any degradation in the noise performance of the adc. the clock inputs (clkp, clkn) are internally biased to 1.15 v and accept a typical 0.5v p-p differential signal swing (figure 4). see the differential, ac-coupled lvpecl-compatible clock input section for more circuit details on how to drive clkp and clkn appropriately. although not recom- mended, the clock inputs also accept a single-ended input signal. the max1214n also features an internal clock-manage-ment circuit (duty-cycle equalizer) that ensures the clock signal applied to inputs clkp and clkn is processed to provide a 50% duty-cycle clock signal that desensitizes the performance of the converter to variations in the duty cycle of the input clock source. note that the clock duty-cycle equalizer cannot be turned off externally and requires a minimum 20mhz clock frequency to allow the device to meet data sheet specifications. data clock outputs (dclkp, dclkn) the max1214n features a differential clock output,which can be used to latch the digital output data with an external latch or receiver. additionally, the clock out- put can be used to synchronize external devices (e.g., fpgas) to the adc. dclkp and dclkn are differential outputs with lvds-compatible voltage levels. there is a 3.95ns delay time between the rising (falling) edge of clkp (clkn) and the rising edge of dclkp (dclkn). see figure 5 for timing details. divide-by-2 clock control (clkdiv) the max1214n offers a clock control line (clkdiv),which supports the reduction of clock jitter in a system. connect clkdiv to ognd to enable the adc? internal divide-by-2 clock divider. data is now updated at one- half the adc? input clock rate. clkdiv has an internal pulldown resistor and can be left open for applications that require this divide-by-2 mode. connecting clkdiv to ov cc disables the divide-by-2 mode. max1214n referencebuffer adc full scale = reft - refb reft: top of reference ladder.refb: bottom of reference ladder. 1v av cc av cc / 2 g control line to disable reference buffer reference- scaling amplifier refio refadj* 0.1 f 100 ? * *refadj maybe shorted to agnd directly. reft refb figure 3. simplified reference architecture downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications ______________________________________________________________________________________ 13 system timing requirements figure 5 shows the relationship between the clock input and output, analog input, sampling event, and data out- put. the max1214n samples on the rising (falling) edge of clkp (clkn). output data is valid on the next rising (falling) edge of the dclkp (dclkn) clock, but has an internal latency of 11 clock cycles. digital outputs (d0p/n?11p/n, dclkp/n, orp/n) and control input t /b digital outputs d0p/n?11p/n, dclkp/n, and orp/nare lvds compatible, and data on d0p/n?11p/n is presented in either binary or two?-complement format (table 1). the t /b control line is an lvcmos-compati- ble input, which allows the user to select the desiredoutput format. pulling t /b low outputs data in two? complement and pulling it high presents data in offsetbinary format on the 12-bit parallel bus. t /b has an internal pulldown resistor and may be left unconnected in applications using only two?-complement output for- mat. all lvds outputs provide a typical 0.325v voltage swing around a 1.2v common-mode voltage, and must be terminated at the far end of each transmission line pair (true and complementary) with 100 ? . apply a 1.7v to 1.9v voltage supply at ov cc to power the lvds outputs. the max1214n offers an additional differential outputpair (orp, orn) to flag out-of-range conditions, where out-of-range is above positive or below negative full scale. an out-of-range condition is identified with orp (orn) transitioning high (low). note: although a differential lvds output architecture reduces single-ended transients to the supply and ground planes, capacitive loading on the digital out- puts should still be kept as low as possible. using lvds buffers on the digital outputs of the adc when driving larger loads may improve overall performance and reduce system-timing constraints. sampling event inp inn clkn clkp dclkn dclkp d0p/d0n d11p/d11n orp/n t pdl t cpdl - t pdl ~ 0.4 x t sample with t sample = 1 / f sample note: the adc samples on the rising edge of clkp. the rising edge of dclkp can be used to externally latch the output data. nn + 1 n + 10 n - 9 n - 10 n - 1n - 1 n + 11 n + 12 n + 1 n - 11 n - 11 n n - 10 n + 1 n sampling event sampling event sampling event sampling event t latency t cpdl t ad t ch t cl figure 5. system and output timing diagram 2.89k ? av dd agnd clkn clkp 5.35k ? 5.35k ? 5.35k ? figure 4. simplified clock input architecture downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications 14 ______________________________________________________________________________________ applications information fsr adjustments using the internal bandgap reference the max1214n supports a 10% (?%) full-scaleadjustment range. to decrease the full-scale signal range, add an external resistor value ranging from 13k ? to 1m ? between refadj and agnd. adding a variable resistor, potentiometer, or predetermined resis- tor value between refadj and refio increases the fsr of the data converter. figure 6a shows the two possible configurations and their impact on the overall full-scale range adjustment of the max1214n. do not use resistor values of less than 13k ? to avoid instability of the internal gain regulation loop for the bandgap ref- erence. see figure 6b for the resulting fsr for a series of resistor values. table 1. max1214n digital output coding inp analog input voltage level inn analog input voltage level out-of-range orp (orn) binary digital output code (d11p/n?0p/n) two?-complement digital output code (d11p/n?0p/n) > v cm + v fs / 4 < v cm - v fs / 4 1 (0) 1111 1111 1111 (exceeds +fs, or set) 0111 1111 1111 (exceeds +fs, or set) v cm + v fs / 4 v cm - v fs / 4 0 (1) 1111 1111 1111 (+fs) 0111 1111 1111 (+fs) v cm v cm 0 (1) 1000 0000 0000 or 0111 1111 1111 (fs/2) 0000 0000 0000 or 1111 1111 1111 (fs/2) v cm - v fs / 4 v cm + v fs / 4 0 (1) 0000 0000 0000 (-fs) 1000 0000 0000 (-fs) < v cm + v fs / 4 > v cm - v fs / 4 1 (0) 0000 0000 0000 (exceeds -fs, or set) 1000 0000 0000 (exceeds -fs, or set) max1214n referencebuffer adc full scale = reft - refb configuration to increase the fsr of the max1214n reft: top of reference ladder.refb: bottom of reference ladder. 1v av cc av cc / 2 g control line to disable reference buffer reference- scaling amplifier refio refadj 0.1 f reft refb 13k ? to 1m ? max1214n referencebuffer adc full scale = reft - refb configuration to decrease the fsr of the max1214n 1v av cc av cc / 2 g control line to disable reference buffer reference- scaling amplifier refio refadj 0.1 f reft refb 13k ? to 1m ? figure 6a. circuit suggestions to adjust the adc? full-scale range downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications ______________________________________________________________________________________ 15 differential, ac-coupled, lvpecl-compatible clock input the max1214n dynamic performance depends on theuse of a very clean clock source. the phase noise floor of the clock source has a negative impact on the snr performance. spurious signals on the clock signal source also affect the adc? dynamic range. the pre- ferred method of clocking the max1214n is differential- ly with lvds- or lvpecl-compatible input levels. the fast data transition rates of these logic families minimize the clock-input circuitry? transition uncertainty, thereby improving the snr performance. to accomplish this, a 50 ? reverse-terminated clock signal source with low phase noise is ac-coupled into a fast differential receiver such as the mc100lvel16 (figure 7). the receiver produces the necessary lvpecl output levels to drive the clock inputs of the data converter. transformer-coupled, differential analog input drive the max1214n provides the best sfdr and thd withfully differential input signals and it is not recommend- ed to drive the adc inputs in single-ended configura- tion. in differential input mode, even-order harmonics are usually lower since inp and inn are balanced, and fs voltage vs. adjust resistor max1214n fig06b fs adjust resistor (k ? ) v fs (v) 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.341.14 resistor value applied betweenrefadj and refio increases v fs resistor value applied betweenrefadj and agnd decreases v fs 900 800 600 700 200 300 400 500 100 0 1000 figure 6b. fs adjustment range vs. fs adjustment resistor mc100lvel16d agnd ognd d0p/n?11p/n, 0rp/n av cc v clk single-ended input terminal 150 ? 150 ? clkp clkn inpinn ov cc 12 2 8 45 7 6 3 50 ? 10k ? 510 ? 510 ? max1214n 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f figure 7. differential, ac-coupled, pecl-compatible clock input configuration downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications 16 ______________________________________________________________________________________ each of the adc inputs only requires half the signalswing compared to a single-ended configuration. wideband rf transformers provide an excellent solu- tion to convert a single-ended signal to a fully differen- tial signal, required by the max1214n to reach its optimum dynamic performance. apply a secondary- side termination of a 1:1 transformer (e.g., mini-circuit? adt1-1wt) into two separate 24.9 ? resistors. higher source impedance values can be used at the expense of degradation in dynamic performance. this configu- ration optimizes thd and sfdr performance of the adc by reducing the effects of transformer parasitics. however, the source impedance combined with the shunt capacitance provided by a pc board and the adc? parasitic capacitance limit the adc? full-power input bandwidth. to further enhance thd and sfdr performance at highinput frequencies (> 100mhz), a second transformer (figure 8) should be placed in series with the single- ended-to-differential conversion transformer. this trans- former reduces the increase of even-order harmonics at high frequencies. single-ended, ac-coupled analog inputs although not recommended, the max1214n can be used in single-ended mode (figure 9). ac-couple the analog signals to the positive input inp through a 0.1? capacitor terminated with a 49.9 ? resistor to agnd. terminate the negative input inn with a 49.9 ? resistor in series with a 0.1? capacitor to agnd. in single-ended mode, theinput range is limited to approximately half of the fsr of the device, and dynamic performance usually degrades. agnd ognd d0p/n?11p/n, 0rp/n av cc inp inn ov cc 12 max1214n 24.9 ? 24.9 ? adt1-1wt adt1-1wt 10 ? 10 ? single-ended input terminal 1 2 3 4 5 3 6 5 1 6 12 4 0.1 f 0.1 f 0.1 f 2 agnd ognd d0p/n?11p/n, 0rp/n av cc inp inn ov cc 12 max1214n single-ended input terminal 0.1 f 0.1 f 49.9 ? 1% 49.9 ? 1% figure 8. analog input configuration with back-to-back transformers and secondary-side termination figure 9. single-ended, ac-coupled analog input configuration downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications ______________________________________________________________________________________ 17 grounding, bypassing, and board layout considerations the max1214n requires board-layout design tech- niques suitable for high-speed data converters. this adc provides separate analog and digital power sup- plies. the analog and digital supply voltage pins accept 1.7v to 1.9v input voltage ranges. although both supply types can be combined and supplied from one source, it is recommended to use separate sources to cut down on performance degradation caused by dig- ital switching currents, which can couple into the analog supply network. isolate analog and digital supplies (av cc and ov cc ) where they enter the pc board with separate networks of ferrite beads and capacitors totheir corresponding grounds (agnd, ognd). to achieve optimum performance, provide each supply with a separate network of a 47f tantalum capacitor and parallel combinations of 10f and 1f ceramic capacitors. additionally, the adc requires each supply pin to be bypassed with separate 0.1f ceramic capacitors (figure 10). locate these capacitors directly at the adc supply pins or as close as possible to the max1214n. choose surface-mount capacitors, whose preferred location should be on the same side as the converter to save space and minimize the inductance. if close placement on the same side is not possible, these bypassing capacitors may be routed through vias to the bottom side of the pc board. multilayer boards with separated ground and power planes produce the highest level of signal integrity. consider the use of a split ground plane arranged to match the physical location of analog and digitalground on the adc? package. the two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. the dynamic currents that may need to travel long distances before they are recombined at a com- mon source ground, resulting in large and undesirable ground loops, are a major concern with this approach. ground loops can degrade the input noise by coupling back to the analog front-end of the converter, resulting in increased spurious activity, leading to decreased noise performance. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground. to minimize the coupling of the digital output signals from the analog input, segregate the digital output bus carefully from the analog input circuitry. to further minimize the effects of digital noise coupling, ground return vias can be posi- tioned throughout the layout to divert digital switching currents away from the sensitive analog sections of the adc. this approach does not require split ground planes, but can be accomplished by placing substantial ground connections between the analog front-end and the digital outputs. the max1214n is packaged in a 68-pin qfn-ep pack- age (package code: g6800-4) , providing greater design flexibility, increased thermal dissipation, andoptimized ac performance of the adc. the exposed paddle (ep) must be soldered down to agnd.in this package, the data converter die is attached to an ep lead frame with the back of this frame exposed agnd note: each power-supply pin (analog and digital) should be decoupled with an individual 0.1 f capacitor as close as possible to the adc. bypassing?dc level bypassing?oard level analog power-supply source ognd agnd ognd d0p/n?11p/n, 0rp/n 1 f 10 f 0.1 f 0.1 f 47 f av cc ov cc 12 max1214n av cc digital/outputdriver power- supply source 1 f 10 f4 7 f ov cc figure 10. grounding, bypassing, and decoupling recommendations for the max1214n downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications 18 ______________________________________________________________________________________ at the package bottom surface, facing the pc boardside of the package. this allows a solid attachment of the package to the board with standard infrared (ir) flow soldering techniques. thermal efficiency is one of the factors for selecting a package with an exposed paddle for the max1214n. the exposed paddle improves thermal and ensures a solid ground connection between the adc and the pc board? analog ground layer. considerable care must be taken when routing the digi- tal output traces for a high-speed, high-resolution data converter. keep trace lengths at a minimum and place minimal capacitive loading (less than 5pf) on any digi- tal trace to prevent coupling to sensitive analog sec- tions of the adc. it is recommended running the lvds output traces as differential lines with 100 ? matched impedance from the adc to the lvds load device. static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on anactual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once off- set and gain errors have been nullified. the static linearity parameters for the max1214n are measured using the histogram method with a 10mhz input frequency. differential nonlinearity (dnl) differential nonlinearity is the difference between anactual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. the max1214n? dnl specification is measured with the histogram method based on a 10mhz input tone. dynamic parameter definitions aperture jitter figure 11 shows the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 11). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital sam- ples, the theoretical maximum snr is the ratio of the full- scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum ana- log-to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr [max] = 6.02 x n + 1.76 in reality, other noise sources such as thermal noise,clock jitter, signal phase noise, and transfer function nonlinearities also contribute to the snr calculation and should be considered when determining the signal-to- noise ratio in adc. the snr for the max1214n is speci- fied in decibels (db), however, snr can also be specified in dbfs. to obtain the snr in dbfs, simply subtract the amplitude of the input tone (this number is given in dbfs) at which the snr is measured from the snr number in db. for example, an adc having an snr of 67db resulting from an input tone with amplitude -1dbfs will have an snr of 67 - (-1) = 68dbfs. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig-nal to all spectral components excluding the fundamen- tal and the dc offset. in the case of the max1214n, sinad is computed from a curve fit. hold analog input sampled data (t/h) t/h t ad t aj track track clkn clkp figure 11. aperture jitter/delay specifications downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications ______________________________________________________________________________________ 19 spurious-free dynamic range (sfdr) sfdr is the ratio of the rms amplitude of the carrierfrequency (maximum signal component) to the rms value of the next-largest noise or harmonic distortion component. sfdr is usually measured in dbc with respect to the carrier frequency amplitude or in dbfs with respect to the adc? full-scale range. intermodulation distortion (imd) imd is the ratio of the rms sum of the intermodulationproducts to the rms sum of the two fundamental input tones. this is expressed as: the fundamental input tone amplitudes (v1 and v2) areat -7dbfs. the intermodulation products are the ampli- tudes of the output spectrum at the following frequencies: second-order intermodulation products: f in1 + f in2 , f in2 - f in1 third-order intermodulation products: 2 x f in1 - f in2 , 2 x f in2 - f in1 , 2 x f in1 + f in2 , 2 x f in2 + f in1 fourth-order intermodulation products: 3 x f in1 - f in2 , 3 x f in2 - f in1 , 3 x f in1 + f in2 , 3 x f in2 + f in1 fifth-order intermodulation products: 3 x f in1 - 2 x f in2 , 3 x f in2 - 2 x f in1 , 3 x f in1 + 2 x f in2 , 3 x f in2 + 2 x f in1 full-power bandwidth a large -1dbfs analog input signal is applied to anadc and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. the -3db point is defined as the full-power input bandwidth frequency of the adc. imd vv v v vv im im im imn log ...... = ++++ + ?? ?? ?? ?? 20 1 2 2 2 3 22 1 2 2 2 pin configuration 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 av cc agnd av cc top view av cc ogndov cc orporn d11p d11n d10p d10n 52 53 d9p d9n agndagnd av cc clkn clkp av cc agnd ov cc ognd d0n ov cc d1n d0pd1p d6pd6n ognd ov cc dclkp dclknov cc d5p d5n d4p 35 36 37 d4n d3p d3n agnd inn inp agnd av cc agnd agnd av cc av cc av cc agnd refadj refio agnd 48 d7n av cc 64 agnd 65 66 67 agndagnd av cc 68 t/b 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 d2n d2p 34 33 49 50 d8nd7p ep 51 d8p 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 clkdiv 17 max1214n qfn ep = exposed paddle downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications 20 ______________________________________________________________________________________ 68l qfn.eps c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) for the max1214n, the package code is g6800-4. downloaded from: http:///
max1214n 1.8v, low-power, 12-bit, 210msps adc for broadband applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 21 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. heaney c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) downloaded from: http:///

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